How to execute makefile in Linux?

Executing Makefiles in Linux: A Step-by-Step Guide

Introduction

Makefiles are a powerful tool for automating tasks on Linux systems. They allow you to define a set of commands that can be executed at specific points in your workflow, making it easier to manage complex projects. In this article, we will cover the basics of executing makefiles in Linux, including how to create and run a makefile, and how to troubleshoot common issues.

Creating a Makefile

A makefile is a text file that contains a set of commands that can be executed by the make command. To create a makefile, you can use a text editor or a command-line tool like nano or vim. Here is an example of a simple makefile:

# This is a simple makefile that builds a program



all: hello



hello: hello.c

    gcc -o hello hello.c



clean:

    rm -f hello

Let’s break down what each line does:

• all: hello: This line specifies that the hello target should be built when the all target is executed.
• hello: hello.c: This line specifies that the hello target should be built when the hello target is executed. The hello.c file is the source code for the program.
• clean: rm -f hello: This line specifies that the clean target should be executed when the clean target is executed. The rm -f hello command removes the hello executable file.

Running a Makefile

To run a makefile, you can use the make command followed by the name of the target. Here are some examples:

• make hello: This command builds the hello target.
• make clean: This command removes the hello executable file.
• make all: This command builds the hello and all targets.

Using Make Variables

Makefiles can also use variables to make the code more flexible and reusable. Here is an example of a makefile that uses variables:

# This is a makefile that uses variables



CFLAGS = -Wall -O2

CXXFLAGS = -std=c++11

LDFLAGS = -L/usr/lib -lstdc++ -lm



hello: hello.c

    gcc -o hello $(CFLAGS) hello.c $(LDFLAGS)



clean:

    rm -f hello

In this example, the CFLAGS, CXXFLAGS, and LDFLAGS variables are used to specify the compiler flags and linker flags. The hello target is built using these variables.

Using Makefiles with Multiple Targets

Makefiles can also use multiple targets to make the code more flexible and reusable. Here is an example of a makefile that uses multiple targets:

# This is a makefile that uses multiple targets



hello: hello.c

    gcc -o hello hello.c



clean:

    rm -f hello

In this example, the hello target is built when the hello target is executed. The clean target is built when the clean target is executed.

Troubleshooting Common Issues

Here are some common issues that you may encounter when using makefiles, along with solutions:

• Makefile not building: Check that the make command is being executed correctly. Make sure that the makefile is in the correct location and that the make command is being run with the correct options.
• Makefile not cleaning: Check that the clean target is being executed correctly. Make sure that the clean target is being executed when the make command is run with the clean option.
• Makefile not building multiple targets: Check that the make command is being executed correctly. Make sure that the makefile is in the correct location and that the make command is being run with the correct options.

Conclusion

Executing makefiles in Linux is a powerful tool for automating tasks on Linux systems. By creating a makefile, you can define a set of commands that can be executed at specific points in your workflow, making it easier to manage complex projects. By using variables and multiple targets, you can make the code more flexible and reusable. By troubleshooting common issues, you can ensure that your makefiles are working correctly.

Additional Tips

• Use make with the -j option to build multiple targets at the same time.
• Use make with the -s option to suppress the progress bar.
• Use make with the -p option to print the makefile and its dependencies.
• Use make with the -n option to run the make command without executing it.

Common Makefile Syntax

Here are some common makefile syntaxes:

• all: target1 target2 ...
• target1: dependency1 dependency2 ...
• target1: target2
• target1: target2, target3 ...
• target1: target2, target3, target4 ...

Common Makefile Variables

Here are some common makefile variables:

• CFLAGS: compiler flags
• CXXFLAGS: C++ compiler flags
• LDFLAGS: linker flags
• target1: the target to build
• target2: the target to clean
• target3: the target to build multiple times
• target4: the target to build multiple times with dependencies